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? 2011 microchip technology inc. ds22143c-page 1 mcp6566/6r/6u/7/9 features: ? propagation delay at 1.8v dd : - 56 ns (typical) high-to-low ? low quiescent current: 100 a (typical) ? input offset voltage: 3 mv (typical) ? rail-to-rail input: v ss - 0.3v to v dd + 0.3v ? open-drain output ? wide supply voltage range: 1.8v to 5.5v ? available in single, dual and quad ? packages: sc70, sot-23-5, soic, msop, tssop typical applications: ? laptop computers ? mobile phones ? hand-held electronics ? rc timers ? alarm and monitoring circuits ? window comparators ? multi-vibrators design aids: ? microchip advanced part selector (maps) ? analog demonstration and evaluation boards ? application notes related device: ? push-pull output: mcp6561/1r/1u/2/4 typical application description: the microchip technology, inc. mcp6566/6r/6u/7/9 families of open-drain output comparators are offered in single, dual and quad configurations. these comparators are optimized for low-power 1.8v, single-supply applications with greater than rail-to-rail input operation. the internal input hysteresis eliminates output switching due to internal input noise voltage, reducing current draw. the open-drain output of the mcp6566/6r/6u/7/9 family requires a pull-up resistor and it supports pull-up voltages above and below v dd, which can be used to level shift. the output toggle frequency can reach a typical of 4 mhz (typical) while limiting supply current surges and dynamic power consumption during switching. this family operates with single supply voltage of 1.8v to 5.5v while drawing less than 100 a/comparator of quiescent current (typical). package types v in v out +5v dd r 2 r f r 3 v dd +3v pu mcp656x mcp6567 +ina -ina v ss 1 2 3 4 8 7 6 5 - outa + - + v dd outb -inb +inb mcp6569 +ina -ina v ss 1 2 3 4 14 13 12 11 - outa + - + v dd outd -ind +ind 10 9 8 5 6 7 outb -inb +inb +inc -inc outc + - - + 5 4 mcp6566 1 2 3 - + 5 4 mcp6566r 1 2 3 - + +in v ss out -in v dd +in v dd out -in v ss sot-23-5, sc70-5 soic, msop sot-23-5 soic, tssop 4 1 2 3 5 sot-23-5 v ss v in + v in ? v dd out mcp6566u - + 1.8v low-power open-drain output comparator
mcp6566/6r/6u/7/9 ds22143c-page 2 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds22143c-page 3 mcp6566/6r/6u/7/9 1.0 electrical characteristics 1.1 maximum ratings* v dd - v ss ....................................................................... 6.5v open-drain output.............................................v ss + 10.5v all other inputs and outputs...........v ss ? 0.3v to v dd + 0.3v difference input voltage ......................................|v dd - v ss | output short circuit current .................................... 25 ma current at input pins .................................................. 2 ma current at output and supply pins .......................... 50 ma storage temperature ................................... -65c to +150c ambient temp. with power applied .............. -40c to +125c junction temp............................................................ +150c esd protection on all pins (hbm/mm) ???????????????????? 4 kv/300v *notice: stresses above those listed under ?maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this spec ification is not implied. expo- sure to maximum rating conditions for extended periods may affect device reliability. dc characteristics electrical characteristics: unless otherwise indicated: v dd = +1.8v to +5.5v, v ss = gnd, t a = +25c, v in + = v dd /2, v in - = v ss , and r pull-up = 20 k ? to v pu = v dd (see figure 1-1 ). parameters symbol min typ max units conditions power supply supply voltage v dd 1.8 ? 5.5 v quiescent current per comparator i q 60 100 130 a i out = 0 power supply rejection ratio psrr 63 70 ? db v cm = v ss input input offset voltage v os -10 ? 3+10mvv cm = v ss ( note 1 ) input offset drift ? v os / ? t? ? 2?v/cv cm = v ss input offset current i os ? ? 1? pav cm = v ss input bias current i b ?1 ?pat a = +25c, v in - = v dd /2 ?60 ? pat a = +85c, v in - = v dd /2 ? 1500 5000 pa t a = +125c, v in - = v dd /2 input hysteresis voltage v hyst 1.0 ? 5.0 mv v cm = v ss ( notes 1 , 2 ) input hysteresis linear temp. co. tc 1 ?10 ?v/c input hysteresis quadratic temp. co. tc 2 ?0.3 ?v/c 2 common-mode input voltage range v cmr v ss ? 0.2 ? v dd +0.2 v v dd = 1.8v v ss ? 0.3 ? v dd +0.3 v v dd = 5.5v common-mode rejection ratio cmrr 54 66 ? db v cm = -0.3v to v dd +0.3v, v dd = 5.5v 50 63 ? db v cm = v dd /2 to v dd +0.3v, v dd = 5.5v 54 65 ? db v cm = -0.3v to v dd /2, v dd = 5.5v common mode input impedance z cm ?10 13 ||4 ? ? ||pf differential input impedance z diff ?10 13 ||2 ? ? ||pf note 1: the input offset voltage is the center of the input-referred tr ip points. the input hysteresis is the difference between the input-referred trip points. 2: v hyst at different temperatur es is estimated using v hyst (t a ) = v hyst @ +25c + (t a - 25c) tc 1 + (t a - 25c) 2 tc 2 . 3: limit the output current to absolute maximum rating of 50 ma. 4: the pull-up voltage for the open drain output v pull_up can be as high as the absolute maximum rating of 10.5v. in this case, i oh_leak can be higher than 1 a (see figure 2-30 ).
mcp6566/6r/6u/7/9 ds22143c-page 4 ? 2011 microchip technology inc. push-pull output pull-up voltage v pull_up 1.6 ? 5.5 v high level output voltage v oh ??v pull_up v (see figure 1-1 ) ( notes 3 , 4 ) high level output current leakage i oh_leak ?? 1 a note 4 low level output voltage v ol ??0.6 vi out = 3ma/8ma @ v dd = 1.8v/5.5v short circuit current ( notes 3 ) i sc ? 30 ? ma not to exceed absolute max. rating output pin capacitance c out ?8 ? pf dc characteristics (continued) electrical characteristics: unless otherwise indicated: v dd = +1.8v to +5.5v, v ss = gnd, t a = +25c, v in + = v dd /2, v in - = v ss , and r pull-up = 20 k ? to v pu = v dd (see figure 1-1 ). parameters symbol min typ max units conditions note 1: the input offset voltage is the center of the input-referred tr ip points. the input hysteresis is the difference between the input-referred trip points. 2: v hyst at different temperatur es is estimated using v hyst (t a ) = v hyst @ +25c + (t a - 25c) tc 1 + (t a - 25c) 2 tc 2 . 3: limit the output current to absolute maximum rating of 50 ma. 4: the pull-up voltage for the open drain output v pull_up can be as high as the absolute maximum rating of 10.5v. in this case, i oh_leak can be higher than 1 a (see figure 2-30 ). ac characteristics electrical characteristics: unless otherwise indicated,: unless otherwise indicated,: v dd = +1.8v to +5.5v, v ss = gnd, t a = +25c, v in+ = v dd /2, v in- = v ss , r pull-up = 20 k ? to v pu = v dd , and c l = 25 pf (see figure 1-1 ). parameters symbol min typ max units conditions propagation delay high-to-low,100 mv overdrive t phl ?5680 nsv cm = v dd /2, v dd = 1.8v ?3480 nsv cm = v dd /2, v dd = 5.5v output fall time t f ?20? ns maximum toggle frequency f tg ?4?mhzv dd = 5.5v ?2?mhzv dd = 1.8v input voltage noise e ni ?350?v p - p 10 hz to 10 mhz ( note 1 ) note 1: eni is based on spice simulation. 2: rise time t r and t plh depend on the load (r l and c l ). these specification are valid for the specified load only. temperature specifications electrical characteristics: unless otherwise indicated: v dd = +1.8v to +5.5v and v ss = gnd. parameters symbol min typ max units conditions temperature ranges specified temperature range t a -40 ? +125 c operating temperature range t a -40 ? +125 c storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, sc70-5 ? ja ? 331 ? c/w thermal resistance, sot-23-5 ? ja ?220.7? c/w thermal resistance, 8l-msop ? ja ?211?c/w thermal resistance, 8l-soic ? ja ?149.5? c/w thermal resistance, 14l-soic ? ja ?95.3? c/w thermal resistance, 14l-tssop ? ja ? 100 ? c/w
? 2011 microchip technology inc. ds22143c-page 5 mcp6566/6r/6u/7/9 1.2 test circuit configuration this test circuit configuration is used to determine the ac and dc specifications. figure 1-1: ac and dc test circuit for the open-drain output comparators. v dd v ss = 0v 200 k ? 200 k ? r pu v out v in = v ss 25 pf v pu = v dd 20 k ? i out mcp656x
mcp6566/6r/6u/7/9 ds22143c-page 6 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds22143c-page 7 mcp6566/6r/6u/7/9 2.0 typical performance curves note: unless otherwise indicated, v dd = +1.8v to +5.5v, v ss = gnd, t a = +25c, v in + = v dd /2, v in ? = gnd, r l = 20 k ? to v pu = v dd , and c l = 25 pf. figure 2-1: input offset voltage. figure 2-2: input offset voltage drift. figure 2-3: input vs. output signal, no phase reversal. figure 2-4: input hysteresis voltage. figure 2-5: input hysteresis voltage drift - linear temp. co. (tc1). figure 2-6: input hysteresis voltage drift - quadratic temp. co. (tc2). note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0% 10% 20% 30% 40% 50% -10 -8 -6 -4 -2 0 2 4 6 8 10 v os (mv) occurrences (%) v dd = 1.8v v cm = v ss avg. = -0.1 mv stdev = 2.1 mv 3588 units v dd = 5.5v v cm = v ss avg. = -0.9 mv stdev = 2.1 mv 3588 units 0% 10% 20% 30% 40% 50% 60% -60 -48 -36 -24 -12 0 12 24 36 48 60 v os drift (v/c) occurrences (%) v cm = v ss avg. = 0.9 v/c stdev = 6.6 v/c 1380 units t a = -40c to +125c -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 time (3 s/div) v out (v) v in - v out v dd = 5.5v v in + = v dd /2 0% 5% 10% 15% 20% 25% 30% 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v hyst (mv) occurrences (%) v dd = 1.8v avg. = 3.4 mv stdev = 0.2 mv 3588 units v dd = 5.5v avg. = 3.6 mv stdev = 0.1 mv 3588 units 0% 10% 20% 30% 40% 50% 60% 02468101214161820 v hyst drift, tc1 (v/c) occurrences (%) 1380 units t a = -40c to 125c v cm = v ss v dd = 5.5v avg. = 10.4 v/c stdev = 0.6 v/c v dd = 1.8v avg. = 12 v/c stdev = 0.6 v/c 0% 10% 20% 30% -0.50 -0.25 0.00 0.25 0.50 0.75 1.00 v hyst drift, tc2 (v/c 2 ) occurrences (%) v dd = 5.5v avg. = 0.25 v/c 2 stdev = 0.1 v/c 2 v dd = 1.8v avg. = 0.3 v/c 2 stdev = 0.2 v/c 2 1380 units t a = -40c to +125c v cm = v ss
mcp6566/6r/6u/7/9 ds22143c-page 8 ? 2011 microchip technology inc. note: unless otherwise indicated, v dd = +1.8v to +5.5v, v ss = gnd, t a = +25c, v in + = v dd /2, v in ? = gnd, r l = 20 k ? to v pu = v dd , and c l = 25 pf. figure 2-7: input offset voltage vs. temperature. figure 2-8: input offset voltage vs. common-mode input voltage. figure 2-9: input offset voltage vs. common-mode input voltage. figure 2-10: input hysteresis voltage vs. temperature. figure 2-11: input hysteresis voltage vs. common-mode input voltage. figure 2-12: input hysteresis voltage vs. common-mode input voltage. -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 -50 -25 0 25 50 75 100 125 temperature (c) v os (mv) v dd = 1.8v v dd = 5.5v v cm = v ss -4.0 -2.0 0.0 2.0 4.0 -0.3 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 v cm (v) v os (mv) v dd = 1.8v t a = +25c t a = +125c t a = +85c t a = -40c -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 v cm (v) v os (mv) v dd = 5.5v t a = -40c t a = +25c t a = +125c t a = +85c 1.0 2.0 3.0 4.0 5.0 -50 -25 0 25 50 75 100 125 temperature (c) v hyst (mv) v dd = 5.0v v dd = 1.8v v cm = v ss 1.0 2.0 3.0 4.0 5.0 -0.3 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 v cm (v) v hyst (mv) v dd = 1.8v t a = +25c t a = +125c t a = +85c t a = -40c 1.0 2.0 3.0 4.0 5.0 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 v cm (v) v hyst (mv) v dd = 5.5v t a = -40c t a = +85c t a = +25c t a = +125c
? 2011 microchip technology inc. ds22143c-page 9 mcp6566/6r/6u/7/9 note: unless otherwise indicated, v dd = +1.8v to +5.5v, v ss = gnd, t a = +25c, v in + = v dd /2, v in ? = gnd, r l = 20 k ? to v pu = v dd , and c l = 25 pf. figure 2-13: input offset voltage vs. supply voltage vs. temperature. figure 2-14: quiescent current. figure 2-15: quiescent current vs. common-mode input voltage. figure 2-16: input hysteresis voltage vs. supply voltage vs. temperature. figure 2-17: quiescent current vs. supply voltage vs temperature. figure 2-18: quiescent current vs. common-mode input voltage. -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 1.5 2.5 3.5 4.5 5.5 v dd (v) v os (mv) t a = -40c t a = +85c t a = +25c t a = +125c 0% 10% 20% 30% 40% 50% 60 70 80 90 100 110 120 130 i q (a) occurrences (%) v dd = 5.5v avg. = 97 a stdev= 4 a 1794 units v dd = 1.8v avg. = 88 a stdev= 4 a 1794 units 60 70 80 90 100 110 120 130 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 v cm (v) i q (a) v dd = 1.8v sweep v in+ ,v in - = v dd /2 sweep v in - ,v in+ = v /2 sweep v in+ ,v in - = v dd /2 sweep v in - ,v in+ = v dd /2 1.0 2.0 3.0 4.0 5.0 1.5 2.5 3.5 4.5 5.5 v dd (v) v hyst (mv) t a = +85c t a = +125c t a = +25c t a = -40c 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 v dd (v) i q (a) t a = -40c t a = +85c t a = +125c t a = +25c 60 70 80 90 100 110 120 130 -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 v cm (v) i q (a) v dd = 5.5v sweep v in+ ,v in - = v dd /2 sweep v in - ,v in+ = v dd /2
mcp6566/6r/6u/7/9 ds22143c-page 10 ? 2011 microchip technology inc. note: unless otherwise indicated, v dd = +1.8v to +5.5v, v ss = gnd, t a = +25c, v in + = v dd /2, v in ? = gnd, r l = 20 k ? to v pu = v dd , and c l = 25 pf. figure 2-19: quiescent current vs. pull-up voltage. figure 2-20: quiescent current vs. toggle frequency. figure 2-21: output headroom vs output current. figure 2-22: quiescent current vs. pull-up to supply voltage difference. figure 2-23: output leakage current vs. pull-up voltage. figure 2-24: output headroom vs output current. 50 75 100 125 150 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 v pu (v) i q (a) i dd spike near v pu = 0.9v v dd = 5.5v v dd = 4.5v v dd = 3.5v v dd = 2.5v v dd = 2.0v v dd = 1.8v 50 100 150 200 250 300 350 400 10 100 1000 10000 100000 100000 0 1e+07 toggle frequency (hz) i q (a) v dd = 1.8v v dd = 5.5v 10 100 1k 10k 100k 1m 10m 100 mv over-drive v cm = v dd /2 r l = open 0db output attenuation 0 200 400 600 800 1000 0.0 3.0 6.0 9.0 12.0 15.0 i out (ma) v ol (mv) v dd = 1.8v t a = +125c t a = +85c t a = +25c t a = -40c 50 75 100 125 150 -4.5 -2.5 -0.5 1.5 3.5 5.5 7.5 9.5 v pu - v dd (v) i q (a) v dd = 3.5 v v dd = 1.8 v v dd = 2.5 v v dd = 2.0 v v dd = 4.5 v v dd = 5.5 v 1 10 100 1,000 10,000 100,000 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 v pu (v) i oh_leak (pa) t a = +25c t a = +85c t a = 0 200 400 600 800 1000 0 5 10 15 20 25 i out (ma) v ol (mv) v dd = 5.5v t a = 125c t a = 125c t a = +85c t a = -40c t a = +25c t a = +125c
? 2011 microchip technology inc. ds22143c-page 11 mcp6566/6r/6u/7/9 note: unless otherwise indicated, v dd = +1.8v to +5.5v, v ss = gnd, t a = +25c, v in + = v dd /2, v in ? = gnd, r l = 20 k ? to v pu = v dd , and c l = 25 pf. figure 2-25: high-to-low propagation delays. figure 2-26: propagation delay vs. input over-drive. figure 2-27: propagation delay vs. supply voltage. figure 2-28: high-to-low propagation delays. figure 2-29: propagation delay vs. temperature. figure 2-30: short circuit current vs. supply voltage vs. temperature. 0% 10% 20% 30% 40% 50% 30 35 40 45 50 55 60 65 70 75 80 prop. delay (ns) occurrences (%) v dd = 1.8v 100 mv over-drive v cm = v dd /2 t phl avg. = 54.4 ns stdev= 2 ns 198 units 10 60 110 160 210 260 1 10 100 1000 over-drive (mv) prop. delay (ns) t phl , v dd = 1.8v t phl , v dd = 5.5v v cm = v dd /2 20 40 60 80 100 120 140 1.5 2.5 3.5 4.5 5.5 v dd (v) prop. delay (ns) t phl , 10 mv over-drive t phl , 100 mv over-drive v cm = v dd /2 0% 10% 20% 30% 40% 50% 30 35 40 45 50 55 60 65 70 75 80 prop. delay (ns) occurrences (%) v dd = 5.5 v 100mv over-drive v cm = v dd / 2 t phl avg. = 33 ns stdev= 1 ns 198 units 20 30 40 50 60 70 80 -50 -25 0 25 50 75 100 125 temperature (c) prop. delay (ns) t phl , v dd = 1.8v 100 mv over-drive v cm = v dd /2 t phl , v dd = 5.5v -120 -80 -40 0 40 80 120 0.0 1.0 2.0 3.0 4.0 5.0 6.0 v dd (v) i sc (ma) t a = -40c t a = +85c t a = +125c t a = +25c t a = -40c t a = +85c t a = +25c t a = +125c
mcp6566/6r/6u/7/9 ds22143c-page 12 ? 2011 microchip technology inc. note: unless otherwise indicated, v dd = +1.8v to +5.5v, v ss = gnd, t a = +25c, v in + = v dd /2, v in ? = gnd, r l = 20 k ? to v pu = v dd , and c l = 25 pf. figure 2-31: propagation delay vs. common-mode input voltage. figure 2-32: propagation delay vs. capacitive load. figure 2-33: input bias current vs. input voltage vs temperature. figure 2-34: propagation delay vs. common-mode input voltage. figure 2-35: propagation delay vs. pull-up resistor. figure 2-36: propagation delay vs. pull-up voltage. 20 30 40 50 60 70 80 0.00 0.50 1.00 1.50 2.00 v cm (v) prop. delay (ns) t phl v dd = 1.8v 100 mv over-drive 0.01 0.1 1 10 100 1000 1 10 100 1000 10000 100000 1e+06 capacitive load (nf) prop. delay (s) 0.001 0.01 0.1 1 10 100 1000 v dd = 5.5v, t phl 100mv over-drive v cm = v dd /2 v dd = 1.8v, t phl 1e-01 1e+01 1e+03 1e+05 1e+07 1e+09 1e+11 -0.8 -0.6 -0.4 -0.2 0 input voltage (v) input current (a) t a = -40c t a = +85c t a = +125c t a = +25c 0.1p 10p 1n 100n 10 1m 10m 20 30 40 50 60 70 80 0.0 1.0 2.0 3.0 4.0 5.0 6.0 v cm (v) prop. delay (ns) t phl v dd = 5.5v 100 mv over-drive 10 100 1000 10000 0.1 1.0 10.0 100.0 r pu (k ? ) prop. delay (ns) t plh t phl 100 mv over-drive v cm = v dd /2 10 100 1000 10000 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v pu (v) prop. delay (ns) t plh, v dd = 5.5v 100 mv over-drive v cm = v dd /2 t plh, v dd = 1.8v t phl, v dd = 1.8v t plh, v dd = 5.5v
? 2011 microchip technology inc. ds22143c-page 13 mcp6566/6r/6u/7/9 note: unless otherwise indicated, v dd = +1.8v to +5.5v, v ss = gnd, t a = +25c, v in + = v dd /2, v in ? = gnd, r l = 20 k ? to v pu = v dd , and c l = 25 pf. figure 2-37: common-mode rejection ratio and power supply rejection ratio vs. temperature. figure 2-38: power supply rejection ratio (psrr). figure 2-39: input offset current and input bias current vs. temperature. figure 2-40: common-mode rejection ratio (cmrr). figure 2-41: common-mode rejection ratio (cmrr). figure 2-42: input offset current and input bias current vs. common-mode input voltage vs. temperature. 70 72 74 76 78 80 -50 -25 0 25 50 75 100 125 temperature (c) cmrr/psrr (db) v cm = -0.3v to v dd + 0.3v v dd = 5.5v cmrr v cm = v ss v dd = 1.8v to 5.5v psrr input referred 0% 5% 10% 15% 20% 25% 30% -600 -400 -200 0 200 400 600 psrr (v/v) occurrences (%) v cm = v ss avg. = 200 v/v stdev= 94 v/v 3588 units 0.1 1 10 100 1000 25 50 75 100 125 temperature (c) i os and i b (pa) i b |i os | 0% 10% 20% 30% -5 -4 -3 -2 -1 0 1 2 3 4 5 cmrr (mv/v) occurrences (%) v dd = 1.8v 3588 units v cm = -0.2v to v dd /2 avg. = 0.5 mv stdev= 0.1 mv v cm = v dd /2 to v dd + 0.2v avg. = 0.7 mv stdev= 1 mv v cm = -0.2v to v dd + 0.2v avg. = 0.6 mv stdev= 0.1 mv 0% 10% 20% 30% -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 cmrr (mv/v) occurrences (%) v dd = 5.5v 3588 units v cm = -0.3v to v dd /2 avg. = 0.2 mv stdev= 0.4 mv v cm = v dd /2 to v dd + 0.3v avg. = 0.03 mv stdev= 0.7 mv v cm = -0.3v to v dd + 0.3v avg. = 0.1 mv stdev= 0.4 mv 0.001 0.01 0.1 1 10 100 1000 10000 0123456 v cm (v) i os and i b (pa) i b @ t a = +125c i b @ t a = +85c |i os| @ t a = +125c |i os |@ t a = +85c v dd = 5.5v
mcp6566/6r/6u/7/9 ds22143c-page 14 ? 2011 microchip technology inc. note: unless otherwise indicated, v dd = +1.8v to +5.5v, v ss = gnd, t a = +25c, v in + = v dd /2, v in ? = gnd, r l = 20 k ? to v pu = v dd , and c l = 25 pf. figure 2-43: output jitter vs. input frequency. 0.1 1 10 100 1000 10000 100 1000 10000 100000 100000 0 1e+07 input frequency (hz) output jitter pk-pk (ns) v dd = 5.5v 100 1k 10k 100k 1m 10m v in+ = 2vpp (sine)
? 2011 microchip technology inc. ds22143c-page 15 mcp6566/6r/6u/7/9 3.0 pin descriptions descriptions of the pins are listed in table 3-1 . table 3-1: pin function table 3.1 analog inputs the comparator non-inverting and inverting inputs are high-impedance cmos inputs with low bias currents. 3.2 digital outputs the comparator outputs are cmos, open-drain digital outputs. they are designed to make level shifting and wired-or easy to implement. 3.3 power supply (v ss and v dd ) the positive power supply pin (v dd ) is 1.8v to 5.5v higher than the negative power supply pin (v ss ). for normal operation, the other pins are at voltages between v ss and v dd . typically, these parts are used in a single (positive) supply configuration. in this case, v ss is connected to ground and v dd is connected to the supply. v dd will need a local bypass capacitor (typically 0.01 f to 0.1f) within 2mm of the v dd pin. these can share a bulk capacitor with nearby analog parts (within 100 mm), but it is not required. mcp6566 mcp6566r mcp6566u mcp6567 mcp6569 symbol description sc70-5, sot-23-5 sot-23-5 sot-23-5 msop, soic soic, tssop 1 1 5 1 1 out, outa digital output (comparator a) 44 3 22v in ?, v ina ? inverting input (comparator a) 33 1 33v in +, v ina + non-inverting input (comparator a) 52 4 84v dd positive power supply ?? ? 5 5v inb + non-inverting input (comparator b) ?? ? 6 6v inb ? inverting input (comparator b) ? ? ? 7 7 outb digital output (comparator b) ? ? ? ? 8 outc digital output (comparator c) ?? ? ? 9v inc ? inverting input (comparator c) ?? ? ?10v inc + non-inverting input (comparator c) 25 2 411v ss negative power supply ?? ? ?12v ind + non-inverting input (comparator d) ?? ? ?13v ind ? inverting input (comparator d) ? ? ? ? 14 outd digital output (comparator d)
mcp6566/6r/6u/7/9 ds22143c-page 16 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds22143c-page 17 mcp6566/6r/6u/7/9 4.0 applications information the mcp6566/6r/6u/7/9 family of open-drain output comparators are fabricated on microchip?s state-of-the-art cmos process. they are suitable for a wide range of high speed applications requiring low- power consumption. 4.1 comparator inputs 4.1.1 normal operation the input stage of this family of devices uses two differential input stages in parallel. this configuration provides three regions of operation, one operates at low input voltages, one at high input voltages, and one at mid input voltage. with this topology, the input voltage range is 0.3v above v dd and 0.3v below v ss , while providing low offset voltage throughout the common mode range. the input offset voltage is measured at both v ss - 0.3v and v dd + 0.3v to ensure proper operation. the mcp6566/6r/6u/7/9 family has internally-set hysteresis v hyst that is small enough to maintain input offset accuracy and large enough to eliminate output chattering caused by the comparator?s own input noise voltage e ni . figure 4-1 depicts this behavior. input offset voltage (v os ) is the center (average) of the (input-referred) low-high and high-low trip points. input hysteresis voltage (v hyst ) is the difference between the same trip points. figure 4-1: the mcp6566/6r/6u/7/9 comparators? internal hysteresis eliminates output chatter caused by input noise voltage. 4.1.2 input voltage and current limits the esd protection on the inputs can be depicted as shown in figure 4-2 . this structure was chosen to protect the input transistors, and to minimize input bias current (i b ). the input esd diodes clamp the inputs when they try to go more than one diode drop below v ss . they also clamp any voltages that go too far above v dd ; their breakdown voltage is high enough to allow normal operation, and low enough to bypass esd events within the specified limits. figure 4-2: simplified analog input esd structures. in order to prevent damage and/or improper operation of these amplifiers, the circuits they are in must limit the currents (and voltages) at the v in + and v in ? pins (see section 1.1 ?maximum ratings*? at the beginning of section 1.0 ?electrical characteristics? ). figure 4-3 shows the recommended approach to protecting these inputs. the internal esd diodes prevent the input pins (v in + and v in ?) from going too far below ground, and the resistors r 1 and r 2 limit the possible current drawn out of the input pin. diodes d 1 and d 2 prevent the input pin (v in + and v in ?) from going too far above v dd . when implemented as shown, resistors r 1 and r 2 also limit the current through d 1 and d 2 . figure 4-3: protecting the analog inputs. -3 -2 -1 0 1 2 3 4 5 6 7 8 time (100 ms/div) output voltage (v) -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 input voltage (10 mv/div) v out v in ? v dd = 5.0v hysteresis bond pad bond pad bond pad v dd v in + v ss input stage bond pad v in ? v 1 r 1 v dd d 1 r 2 ? v ss ? (minimum expected v 2 ) 2ma v out v 2 r 2 r 3 d 2 + ? r 1 ? v ss ? (minimum expected v 1 ) 2ma v pu r 4 mcp656x
mcp6566/6r/6u/7/9 ds22143c-page 18 ? 2011 microchip technology inc. it is also possible to connect the diodes to the left of the resistors r 1 and r 2 . in this case, the currents through the diodes d 1 and d 2 need to be limited by some other mechanism. the resistor then serves as in-rush current limiter; the dc current into the input pins (v in + and v in ?) should be very small. a significant amount of current can flow out of the inputs when the common mode voltage (v cm ) is below ground (v ss ); see figure 4-3 . applications that are high-impedance may need to limit the usable voltage range. 4.1.3 phase reversal the mcp6566/6r/6u/7/9 comparator family uses cmos transistors at the input. they are designed to prevent phase inversion when the input pins exceed the supply voltages. figure 2-3 shows an input voltage exceeding both supplies with no resulting phase inversion. 4.2 open-drain output the open-drain output is designed to make level-shifting and wired-or logic easy to implement. the output stage minimizes switching current (shoot-through current from supply-to-supply) when the output changes state. see figures 2-15 , 2-18 , 2-35 and 2-36 , for more information. 4.3 externally set hysteresis greater flexibility in selecting hysteresis (or input trip points) is achieved by using external resistors. hysteresis reduces output chattering when one input is slowly moving past the other. it also helps in systems where it is best not to cycle between high and low states too frequently (e.g., air conditioner thermostatic control). output chatter also increases the dynamic supply current. 4.3.1 non-inverting circuit figure 4-4 shows a non-inverting circuit for single-supply applications using just two resistors. the resulting hysteresis diagram is shown in figure 4-5 . figure 4-4: non-inverting circuit with hysteresis for single-supply. figure 4-5: hysteresis diagram for the non-inverting circuit. the trip points for figures 4-4 and 4-5 are: equation 4-1: v ref v in v out v dd r 1 r f + - v pu r pu mcp656x v out high-to-low low-to-high v dd v oh v ol v ss v ss v dd v thl v tlh v in v tlh v ref 1 r 1 r f ------- + ?? ?? ?? v ol r 1 r f ------- ?? ?? ?? ? = v thl v ref 1 r 1 r f ------- + ?? ?? ?? v oh r 1 r f ------- ?? ?? ?? ? = where: v tlh = trip voltage from low-to-high v thl = trip voltage from high-to-low
? 2011 microchip technology inc. ds22143c-page 19 mcp6566/6r/6u/7/9 4.3.2 inverting circuit figure 4-6 shows an inverting circuit for single-supply using three resistors. the resulting hysteresis diagram is shown in figure 4-7 . figure 4-6: inverting circuit with hysteresis. figure 4-7: hysteresis diagram for the inverting circuit. in order to determine the trip voltages (v thl and v tlh ) for the circuit shown in figure 4-6 , r 2 and r 3 can be simplified to the thevenin equivalent circuit with respect to v dd , as shown in figure 4-8 . figure 4-8: thevenin equivalent circuit. where: using this simplified circuit, the trip voltage can be calculated using the following equation: equation 4-2: figure 2-21 and figure 2-24 can be used to determine typical values for v oh and v ol . 4.4 bypass capacitors with this family of comparators, the power supply pin (v dd for single supply) should have a local bypass capacitor (i.e., 0.01 f to 0.1 f) within 2 mm for good edge rate performance. 4.5 capacitive loads reasonable capacitive loads (e.g., logic gates) have little impact on propagation delay (see figure 2-32 ). the supply current increases with increasing toggle frequency ( figure 2-20 ), especially with higher capacitive loads. the output slew rate and propagation delay performance will be reduced with higher capacitive loads. v in v out v dd r 2 r f r 3 v dd v pu r pu mcp656x v out high-to-low low-to-high v dd v oh v ol v ss v ss v dd v tlh v thl v in v 23 v out v dd r 23 r f + - v ss v pu r pu mcp656x r 23 r 2 r 3 r 2 r 3 + ------------------ - = v 23 r 3 r 2 r 3 + ------------------ -v dd ? = v thl v oh r 23 r 23 r f + ---------------------- - ?? ?? ?? v 23 r f r 23 r f + --------------------- - ?? ?? + = v tlh v ol r 23 r 23 r f + ---------------------- - ?? ?? ?? v 23 r f r 23 r f + --------------------- - ?? ?? + = where: v tlh = trip voltage from low-to-high v thl = trip voltage from high-to-low
mcp6566/6r/6u/7/9 ds22143c-page 20 ? 2011 microchip technology inc. 4.6 pcb surface leakage in applications where low input bias current is critical, pcb (printed circuit board) surface leakage effects need to be considered. surface leakage is caused by humidity, dust or other contamination on the board. under low humidity conditions, a typical resistance between nearby traces is 10 12 ? . a 5v difference would cause 5 pa of current to flow. this is greater than the mcp6566/6r/6u/7/9 family?s bias current at +25c (1 pa, typical). the easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). the guard ring is biased at the same voltage as the sensitive pin. an example of this type of layout is shown in figure 4-9 . figure 4-9: example guard ring layout for inverting circuit. 1. inverting configuration ( figures 4-6 and 4-9 ): a) connect the guard ring to the non-inverting input pin (v in +). this biases the guard ring to the same reference voltage as the comparator (e.g., v dd /2 or ground). b) connect the inverting pin (v in ?) to the input pad without touching the guard ring. 2. non-inverting configuration ( figure 4-4 ): a) connect the non-inverting pin (v in +) to the input pad without touching the guard ring. b) connect the guard ring to the inverting input pin (v in ?). 4.7 pcb layout technique when designing the pcb layout it is critical to note that analog and digital signal traces are adequately separated to prevent signal coupling. if the comparator output trace is at close proximity to the input traces then large output voltage changes from, v ss to v dd or visa versa, may couple to the inputs and cause the device output to oscillate. to prevent such oscillation, the output traces must be routed away from the input pins. the sc70-5 and sot-23-5 are relatively immune because the output pin out (pin 1) is separated by the power pin v dd /v ss (pin 2) from the input pin +in (as long as the analog and digital traces remain separated throughout the pcb). however, the pinouts for the dual and quad packages (soic, msop, tssop) have out and -in pins (pin 1 and 2) close to each other. the recommended layout for these packages is shown in figure 4-10 . figure 4-10: recommended layout. 4.8 unused comparators an unused amplifier in a quad package (mcp6569) should be configured as shown in figure 4-11 . this circuit prevents the output from toggling and causing crosstalk. it uses the minimum number of components and draws minimal current (see figure 2-15 and figure 2-15 ). figure 4-11: unused comparators. guard ring v ss in- in+ -ina +ina -inb +inb outb outa v ss v dd v dd ? + ? mcp6569
? 2011 microchip technology inc. ds22143c-page 21 mcp6566/6r/6u/7/9 4.9 typical applications 4.9.1 precise comparator some applications require higher dc precision. an easy way to solve this problem is to use an amplifier (such as the mcp6291) to gain-up the input signal before it reaches the comparator. figure 4-12 shows an example of this approach. figure 4-12: precise inverting comparator. 4.9.2 windowed comparator figure 4-13 shows one approach to designing a windowed comparator. the and gate produces a logic ? 1 ? when the input voltage is between v rb and v rt (where v rt > v rb ). figure 4-13: windowed comparator. 4.9.3 bistable multi-vibrator a simple bistable multi-vibrator design is shown in figure 4-14 . v ref needs to be between the power supplies (v ss = gnd and v dd ) to achieve oscillation. the output duty cycle changes with v ref . figure 4-14: bistable multi-vibrator. v ref v dd v dd r 1 r 2 v out v in v ref mcp6291 v pu r pu mcp656x v rt v rb v in v pu r pu v out 1/2 mcp6567 1/2 mcp6567 v dd r 1 r 2 r 3 v ref c 1 v out v pu r pu mcp656x
mcp6566/6r/6u/7/9 ds22143c-page 22 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds22143c-page 23 mcp6566/6r/6u/7/9 5.0 design aids 5.1 microchip advanced part selector (maps) maps is a software tool that helps semiconductor professionals efficiently identify microchip devices that fit a particular design requirement. available at no cost from the microchip web site at www.microchip.com/ maps, the maps is an overall selection tool for microchip?s product portfolio that includes analog, memory, mcus and dscs. using this tool you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. helpful links are also provided for data sheets, purchase, and sampling of microchip parts. 5.2 analog demonstration and evaluation boards microchip offers a broad spectrum of analog demonstration and evaluation boards that are designed to help you achieve faster time to market. for a complete listing of these boards and their corresponding user?s guides and technical information, visit the microchip web site at www.microchip.com/ analogtools. three of our boards that are especially useful are: ? 8-pin soic/msop/tssop/ dip evaluation board, p/n soic8ev ? 14-pin soic/tssop/dip evaluation board, p/n soic14ev ? 5/6-pin sot23 evaluation board, p/n vsupev2 5.3 application notes the following microchip application notes are available on the microchip web site at www.microchip.com and are recommended as supplemental reference resources: ? an895, ?oscillator circuit for rtd temperature sensors?, ds00895 .
mcp6566/6r/6u/7/9 ds22143c-page 24 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds22143c-page 25 mcp6566/6r/6u/7/9 6.0 packaging information 6.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 5-lead sc70 (mcp6566) example: xxnn 5-lead sot-23 (mcp6566, mcp6566r) example: xxnn jy25 bj25 8-lead soic (150 mil) (mcp6567) example: xxxxxxxx xxxxyyww nnn mcp6567 e sn ^^ 1040 256 3 e 8-lead msop (mcp6567) example: xxxxxx ywwnnn 6567e 040256 device code mcp6566t jynn mcp6566rt jznn mcp6566ut wlnn note: applies to 5-lead sot-23.
mcp6566/6r/6u/7/9 ds22143c-page 26 ? 2011 microchip technology inc. package marking information (continued) 14-lead tssop (mcp6569) xxxxxxxx yyww nnn example: mcp6569e 1040 256 14-lead soic (150 mil) (mcp6569) example: xxxxxxxxxx yywwnnn xxxxxxxxxx mcp6569 1040256 e/sl ^^ 3 e
? 2011 microchip technology inc. ds22143c-page 27 mcp6566/6r/6u/7/9 d b 1 2 3 e1 e 4 5 ee c l a1 aa2
mcp6566/6r/6u/7/9 ds22143c-page 28 ? 2011 microchip technology inc.
? 2011 microchip technology inc. ds22143c-page 29 mcp6566/6r/6u/7/9 n b e e1 d 1 2 3 e e1 a a1 a2 c l l1
mcp6566/6r/6u/7/9 ds22143c-page 30 ? 2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2011 microchip technology inc. ds22143c-page 31 mcp6566/6r/6u/7/9 d n e e1 note 1 1 2 e b a a1 a2 c l1 l
mcp6566/6r/6u/7/9 ds22143c-page 32 ? 2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2011 microchip technology inc. ds22143c-page 33 mcp6566/6r/6u/7/9 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp6566/6r/6u/7/9 ds22143c-page 34 ? 2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2011 microchip technology inc. ds22143c-page 35 mcp6566/6r/6u/7/9
mcp6566/6r/6u/7/9 ds22143c-page 36 ? 2011 microchip technology inc. note 1 n d e e1 1 23 b e a a1 a2 l l1 c h h
? 2011 microchip technology inc. ds22143c-page 37 mcp6566/6r/6u/7/9
mcp6566/6r/6u/7/9 ds22143c-page 38 ? 2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2011 microchip technology inc. ds22143c-page 39 mcp6566/6r/6u/7/9 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp6566/6r/6u/7/9 ds22143c-page 40 ? 2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2011 microchip technology inc. ds22143c-page 41 mcp6566/6r/6u/7/9 appendix a: revision history revision c (february 2011) the following is the list of modifications: 1. replaced the mcp5468 package name with the correct mcp6567 package name on page 1 and in table 3-1 . revision b (august 2009) the following is the list of modifications: 1. added mcp6566u throughout the document. 2. updated package outline drawings. revision a (march 2009) ? original release of this document.
mcp6566/6r/6u/7/9 ds22143c-page 42 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds22143c-page 43 mcp6566/6r/6u/7/9 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: mcp6566t: single comparator (tape and reel) (sc70, sot-23) mcp6566rt: single comparator (tape and reel) (sot-23 only) mcp6566ut: single comparator (tape and reel) (sot-23 only) mcp6567: dual comparator mcp6567t: dual comparator (tape and reel) mcp6569: quad comparator mcp6569t: quad comparator (tape and reel) temperature range: e= -40 ? c to +125 ? c package: lt = plastic small outline transistor (sc70), 5-lead ot = plastic small outline transistor (sot-23), 5-lead ms = plastic micro small outline transistor, 8-lead sn = plastic small outline transistor, 8-lead st = plastic thin shrink small outline transistor, 14-lead sl = plastic small outline transistor, 14-lead examples: a) mcp6566t-e/lt: tape and reel, extended temperature, 5ld sc70 package. b) mcp6566t-e/ot: tape and reel extended temperature, 5ld sot-23 package. a) mcp6566rt-e/ot: tape and reel extended temperature, 5ld sot-23 package. a) mcp6566ut-e/ot: tape and reel extended temperature, 5ld sot-23 package. a) mcp6567-e/ms: extended temperature 8ld msop package. b) mcp6567-e/sn: extended temperature 8ld soic package. a) mcp6569t-e/sl: tape and reel extended temperature 14ld soic package. b) mcp6569t-e/st: tape and reel extended temperature 14ld tssop package. part no. x /xx package temperature range device ?
mcp6566/6r/6u/7/9 ds22143c-page 44 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds22143c-page 45 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2011, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-60932-892-4 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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